1. Field of the Invention
This invention relates generally to semiconductor devices, and, more particularly, to characterizing arrays using cell-based timing elements derived from a transistor-level design for a semiconductor device.
2. Description of the Related Art
Modern integrated circuits typically include tens of thousands of individual transistors. The precise number of transistors, as well as the interconnections between the transistors and/or other elements of the integrated circuit, may be specified in a circuit design. In principle, circuit designs could be tested by fabricating a device based on the circuit design and then directly testing the device to make sure that it performs in the expected manner. However, configuring a semiconductor fabrication facility to fabricate the device and then fabricating one or more devices for testing would cost an undesirably large amount of time and/or money. Accordingly, circuit designs are typically tested by simulating the timing of the circuit design.
One technique for simulating a circuit design determines the circuit timing by simulating the interaction of individual transistors in the circuit. This technique is known as “transistor-level simulation.” The most popular program for transistor-level simulation is the Simulation Program with Integrated Circuit Emphasis (SPICE), which was developed at Berkeley starting in the 1970s, and is widely available in multiple forms today. Transistor-level simulation programs use a matrix-based technique for determining the circuit timing, which may make the transistor-level approach unwieldy and/or impractical for relatively large circuits, e.g. circuits that have in excess of about 10,000 transistors. Furthermore, transistor-level simulations typically require that the design engineer specify a particular path through the circuit design, e.g. in the form of a vector, in order to determine the time delay(s) associated with the path. Relatively large circuits may have numerous paths and the design engineer may have difficulty determining the correct path and, in some cases, may analyze an incorrect path. Some faster versions of transistor-level simulations may assume one or more heuristics in order to partition the circuit design.
Alternatively, the circuit design may be specified in terms of one or more cells. A cell-based circuit design specifies the properties of one or more cell elements and the interconnections between the cell elements. For example, the cell elements may include NAND gates, NOR gates, and the like. The cell-based circuit design may then specify the interconnections between the NAND gates and/or the NOR gates that are necessary to implement the logic and/or functions of the desired device. The particular arrangements of transistors that may be used to implement the cell elements are not typically specified by the cell-based circuit design. Instead, the transistor-level implementation is left undefined and design engineers are free to choose from among many possible transistor-level implementations of the cell elements.
Cell-based circuit designs may be simulated using static timing techniques. Static timing is a vectorless technique and so there is no need for the design engineer to specify a timing path through the circuit. Instead, a static timing simulator examines all possible paths through the circuit design. However, static timing cannot be applied directly to a transistor-level circuit design. Some static timing simulators include internal modules that attempt to convert transistor-level circuit designs to cell-based designs by modeling the transistor-level circuit design. However, when compared to cell-based static timing, these approaches typically have a low capacity and low control over the simulation. Furthermore, the models that are employed may impose a number of restrictions on the simulation. For example, the cells are only valid in context in which the cell is used.
Memory arrays such as synchronous random access memory (SRAM) arrays are particularly difficult to analyze because they include a very large number of individual transistors and the memory array circuits must satisfy very tight timing constraints. Transistor-level static timing tools typically have speed and capacity restrictions that reduce the accuracy of the timing analysis. Consequently, transistor-level static timing tools are generally considered to be too inaccurate to handle the bit cell and/or sense amplifier delays present in memory elements. Cell-based static timing tools are generally considered more accurate, but the efficacy of the cell-based static timing tools is limited by the characterization of the individual cells. In the case of memory arrays such as those found in microprocessor caches, defining the cells from a transistor-level design may be difficult or impossible because the extracted netlist is a flat transistor netlist that is not typically amenable to analysis by a cell-based static timing tool.
The parameters of the cells in a memory array, such as timing parameters, may be estimated by creating a critical path model and inserting extracted layout schematics as necessary. However, this technique is prone to error because circuit designers must estimate parasitics associated with some elements in the transistor-level design. Alternatively, the cells may be characterized by specifying a single path through the memory array, e.g., using a path pruning algorithm. This technique is also prone to error because the path pruning algorithm does not consider paths other than the specified path through the memory array. Consequently, the timing analysis of the memory array may be flawed if the circuit designer has not specified the correct (or optimal) path through the memory array. For example, performing the timing analysis based on cells defined using the path pruning algorithm may not detect portions (or corners) of the memory array that do not meet the strict timing margins for the memory array.
Columns within the memory array may also include elements that are not included in conventional models of cells that may be analyzed using conventional cell-based static timing techniques. For example, a column in a memory array typically includes sense amplifiers and read/write circuitry to read out (or write in) data stored in the bit cells of the column. Furthermore, conventional estimates of the properties of a cell allow the circuit designer to specify the order of particular events (such as the order of signals asserted on different lines), but do not typically allow the designer to define time delays between these events. For example, conventional techniques for characterizing cells do not specify setup/hold times of control signals (e.g., sense amplifier fire, read column select, right enable, midline precharge, sense amplifier precharge, word lines, and the like) in relation to one another. Thus, conventional cell-based static timing tools may not be able to ensure that the transistor-level design of a memory array will satisfy the required timing constraints.